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Stage 5G Base Station Layer 1 VHDL Design

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Corporate Services
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MN Mobile Networks
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1900000JGG Requisition #
Nokia is a global leader in the technologies that connect people and things. With state-of-the-art software, hardware and services for any type of network, Nokia is uniquely positioned to help communication service providers, governments, and large enterprises deliver on the promise of 5G, the Cloud and the Internet of Things. 
Serving customers in over 100 countries, our research scientists and engineers continue to invent and accelerate new technologies that will increasingly transform the way people and things communicate and connect.
Nokia is an equal opportunity employer that is commited to diversity and inclusion.
At Nokia, employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law.

Internship topic:
Based on a High Level synthesis IP part of 5G Data Shared Channel, recode it in HDL (Verilog/VHDL) and compare the result of synthesis of both implementation using Altera/intel Quartus synthesis tool. It can be done in several sub-modules to analyze which profile of sub-block gains the most being optimized by synthetizing the RTL with HDL code.Benefit of the internship for Nokia is to evaluate complexity vs area vs coding time to help designers to choose between C-HLS and HDL code and provide some generic modules to quickly implement a hybrid C-HLS/HDL RTL.

 

Sub-tasks:

·       Verify in a stand-alone UVM SystemVerilog environment (may need to add some verification tool => ready/vld random/full throughput).

·       Synthetize the C-HLS Top module after removing the sub-module that is tested in HDL.

·       Integrate the new sub-module and the top re-synthetized in order to have an equivalent of initial C-HLS Top.

·       Verify in the UVM environment the top (normally already in place => would just need to run without big optimizations).

·       Compare both implementations.

 

The internship work can be processed on different sub-blocks with various profiles to analyze where the results are the best.

 

 

Skills required :

·       HDL coding (verilog/VHDL)

·        FPGA implementation, RTL knowledges

·        C language

·        BONUS: object-oriented programming (for UVM SystemVerilog customization using the existing environment)

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Nokia is an equal opportunity employer that is committed to diversity and inclusion. At Nokia, employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law.