FPGA RTL Development or Verification Engineer
Qualifications
v Bachelor or above, major in
Telecommunication, Electronic Engineering, Computer Science or related. v 3+ years FPGA/ASIC design or verification
experience, familiar with hardware design/verification language such as
Verilog, VHDL, System Verilog and synthesis, implementation, simulation
tools. v Better to have knowledge on digital signal
processing technology. v Better to have knowledge on RAN system
architecture. v Strong communication skill. v Highly responsible, self-motivated and
proactive working attitude. v Good team working, willing to contribute to
team’s success. v Fluent in both oral and written English. |