FPGA Physical Layer Arch & Design
specific skills required:
- Knowledgeable in 5G NR, LTE and other advanced wireless radio access protocols and signal processing
- Able to architect radio access baseband solutions across subsystem components of SoC, processors, FPGA, DSP, high-speed fronthaul and backhaul interfaces. System modeling skills to validate the architecture approach. Design skills to implement some of individual subsystems as mentioned above.
- Highly skilled FPGA designer familiar with recent Xilinx or Intel-Altera family of parts and tools, particularly complex systems operating at very speeds.
- Able to implement physical layer or data link (L2) in dedicated HW subsystems
- Able to simulate functional design using appropriate simulation tools.
- Proficient in using state-of-the art synthesis tools from high level design languages (VHDL, Verilog)
- Proficient in debugging real-time systems
- Experience implementing above functionality in ASIC tool chain is a plus.
- Able to write low level sw so as to interface and test FPGA
- Proficient in designs running at very high speeds including wireless access and backhaul/fronthaul at greater than 10 Gbps.
- 7+ years experience