ASIC SoC/IP design engineer
Qualifications:
- Engineer either motivated in RTL VHDL/Verilog design development or RTL verification on IP level
- Complete understanding of the SoC (ASIC/FPGA) design flow and process,
- Knowledge of SoC design and verification tools (SystemVerilog / UVM)
- Matlab/Simulink modelling and HW ref model creation knowledge and skills
- Good spoken and written technical English.